Experimental High Level Synthesis (HLS) from prototype based object oriented scripting language (Karuta) to RTL (Verilog) which might become useful for FPGA development. Project designed its own language Karuta just only for RTL design instead of reusing existing languages.
>800 commits

Some of following features are incorporated in the language constructs to make it easy to use:

∙ Prototype based object system to model design structures
∙ Flexible data types
◦ Integer with width. Custom operators for defined data types like FP16
∙ Communication primitives
◦ Threads, mailboxes, channels and so on
◦ AXI, RPC like handshake, GPIO, embedded verilog and so on
∙ HDL generators and optimizers
◦ Generates Verilog or HTML
◦ SSA based optimizers
◦ Scheduling and allocation based on device parameters

https://github.com/nlsynth/karuta

#HLS #Karuta #iroha #verilog

Knowledge base related to Xilinx SoC products contributed by Xilinx staff. Most info useful for SW engineer who use Xilinx SoC:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/overview

#Xilinx #MicroBlaze #ZYNQ #Linux #SoC #MPSoC

New book related to MPSoCs. Buy from Amazon or download the FREE e-book and build your knowledge of Zynq UltraScale+

https://www.zynq-mpsoc-book.com

#MPSoCs #ZYNQ #ML #PYNQ

Several videos about HBM vs GDDR6:

● HBM vs GDDR6: look at two different memory options, and the pros and cons of each
● GDDR6–HBM2 Tradeoffs: What type of DRAM works best where
● Latency Under Load: HBM2 vs GDDR6

#HBM2 #GDDR6 #DRAM #latency #tradeoff

Alterrnative of datasheets for lazy designers in CLI

Just find required P/N:

get_parts [-regexp] [-filter <arg>] <patterns>

And getting some pieces of info related to P/N:

report_property [get_parts <parts>]

#xilinx #FPGA #vivado #datasheet #tcl

Vivado 2019.1 is available now

Download, WhatsNew, Videos

#Xilinx #Vivado #HLS

Presentation: Introduction to ASIC design for FPGA developers

#doc #ASIC #FPGA #beginner

Wave Computing and Imperas introduce new MIPS Open Simulator MIPSOpenOVPsim - is a MIPS system architecture simulator, available at no cost, which implements a complete single-core CPU. MIPSOpenOVPsim is an entry ramp for software development, SoC testing and verification.

MIPSOpenOVPsim offers:
● A jump-start to software and firmware development during the SoC design cycle
● Early-stage implementation testing and Design Verification (DV) of MIPS CPU core designs
● Acceleration of compliance testing by providing a reference environment

MIPSOpenOVPsim helps SoC developers by providing a comprehensive testing platform for all MIPS Open specifications and extensions including:
● The MIPS 32 and 64-bit ISA Rev6 licensed under MIPS Open
● MIPS SIMD Extensions v1.0
● MIPS DSP Extensions
● MIPS Multi-Threading (MT)
● MIPS MCU
● microMIPS Architecture
● MIPS Virtualization (VZ)

Further details and download are available.

#MIPS #MIPSOpen #simulator #verification

Formal Verification with SymbiYosys and Yosys-SMTBMC
◦ Presentation Slides
◦ Examples

Investigating and Verifying Hardware Designs with Formal Open Source Tools
◦ Presentation Slides
◦ Examples

References:
==========

Yosys family:
◦ Yosys - a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains
◦ SymbiYosys - a front-end driver program for Yosys-based formal hardware verification flows

SAT and SMT solvers:
◦ Z3 Theorem Prover
◦ Yices2 SMT Solver
◦ Boolector
◦ ABC
◦ super_prove
◦ Avy

#Formal #Verification #SymbiYosys #Yosys #solver #publication #opensource

A padring generator for ASIC.
Tool makes padrings for ASICs using a LEF file and a placement/configuration file. The padrings can be output in GDS2, DEF and/or SVG format.

https://github.com/YosysHQ/padring

#ASIC #phydesign #padring #LEF #GDSII #DEF

ASIC Pinout Drawer - a simple pin assignment generator for IC case.

Input:
◦ CSV or AsciiDoc table

Output:
◦ SVG or PNG drawing

https://github.com/iDoka/asic-pinout-drawer

#ASIC #techdoc #techwriting #datasheet #asciidoc #svg

diearea - a script for analyzing and graphical representation of area occupied by some part of hierarhical design in Synopsys DC (based on dc_shell report parsing).

https://github.com/dmitrodem/sizefs

#ASIC #DC #tcl #area #report #sizefs #json

PyMTL - an open-source python-based unified framework for multi-level hardware modeling and vertically integrated computer architecture research.

PyMTL that aims to close this computer architecture research methodology gap by providing a unified design environment for functional-level (FL), cycle-level (CL), and register-transfer-level (RTL) modeling. PyMTL leverages the Python programming language to create a highly productive domain-specific embedded language for concurrent-structural modeling and hardware design.

A custom JIT engine automatically generates optimized C++ for CL and RTL models. To reduce the performance impact of the remaining unspecialized code, Sim JIT combines with an off-the-shelf Python interpreter with a meta-tracing JIT compiler (PyPy). Sim JIT+PyPy provides speedups of up to 72× for CL models and 200× for RTL models.

◦ Paper
◦ Tutorial + Examples
◦ Sources

#PyMTL #JIT #framework #python #modeling #verilator

Did you know that Icarus Verilog includes a non-standard random number generator as a built-in?

$mti_random()
$mti_dist_uniform

These functions are similar to the IEEE1364 standard $random functions, but they use the Mersenne Twister (MT19937) algorithm. This is considered an excellent random number generator, but does not generate the same sequence as the standardized $random.

#iverilog #simulation #verilog #random #RNG

BD_SHELL - is like a UNIX command line shell, but for manually writing and reading FPGA|ASIC registers on a 32bit Local Bus. Supports scripting of course and dumping register contents to a file. It works alongside SUMP2 as a diagnostic tool for chip bringup and debugging.

Fully cross platform compatible and much easier to maintain. BD_SHELL is part of "Backdoor" suite of tools for FPG/A/SIC diagnostics over a simple 2-pin FTDI cable for 1 Mbps UART communications using the Mesa Bus Protocol. The bd_server.py TCP server supports other links such a PCIe, SERDES, whatever you have that Python can talk to, bd_server.py can adapt to.

https://github.com/blackmesalabs/bd_shell

#debug #backdoor #FTDI #python #powershell

Quick & dirty approach to detect/prevent any attempt to JTAG access. The output signal might will use an almost infinite number of possible options, such as:

◦ Reset the internal MMCM/PLLs
◦ Gate off any internal clocks
◦ Drive the GSR or GTS inputs on the STARTUPEx primitive

#FPGA #Xilinx #JTAG #TamperDetection #protection #security

VHD2VL - free and opensource translator for synthesizable VHDL into Verilog 1995/2001. It does not support the full VHDL grammar - most of the testbench related features have been left out. Syntax and semantics are not carefully checked. vhd2vl assumes that the input is error-free.
Vhd2vl is written using lex (actually Flex), yacc (actually Bison), and C.

The most important VHDL constructs missing from this version are
◦ packages
◦ structures
◦ functions
◦ strings
◦ attributes

Project page + sources

#VHDL #Verilog #converter #translator #flex #bison