Automated flow for compressing convolution neural networks for efficient edge-computation with FPGA
#FPGA #NN #ML #CNN #YOLO #LeapMind #TensorFlow

LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks
#FPGA #NN #ML #LegUp #LLVM #DNN #Python #XLA #TensorFlow

CLaaS - Custom Logic as a Service.
This solution, it significantly reduces the complexity of developing a hardware-accelerated application, bringing the platform within the reach of everyone, including startups, open-source enthusiasts and makers. With the framework, you can stream data directly between your custom FPGA kernel and application using standard websockets.

https://github.com/alessandrocomodi/fpga-webserver

#CLaaS #FPGA #web #framework #WebSocket #AWS

OpenSTA - the engine for gate level static timing verifier. As a stand-alone executable it can be used to verify the timing of a design using standard file formats. OpenSTA uses a TCL command interpreter to read the design, specify timing constraints and print timing reports.

Sources, Docs

#TCL #STA #sdc #sdf #spef #timing #analyze #netlist

The OpenROAD team also has several amazing projects, e.g.:

◦ RePlAce - RePlAce global placement tool
◦ FastRoute4-lefdef - LEF/DEF/Rsyn-based router
◦ OpenDP - Open Source Detailed Placement engine
◦ TritonCTS - Srcs and calibration scripts for clock tree synthesis
◦ magic - OpenROAD specific Magic VLSI Layout Tool
◦ ioPlacer - IO and Pin Placer for Floorplan-Placement Subflow

#ASIC #TCL

Xilinx Vitis slides from today's presentation:

Bring Your Applications to Life with Vitis

#Xilinx #Vitis #HLS #FaaS #AI #Alveo #SDAccel #SDSoC

#VitisAI has been released today at the #xdf2019 and is available for download now.

In a nutshell: it is the tool that takes your trained #tensorflow or #caffe model and optimises it for your #Xilinx hardware.
Or very simply spoken: the turbocharge for #versal-devices and their AI engines.

HDL Checker - a language server that wraps VHDL/Verilg/SystemVerilog tools that aims to reduce the boilerplate code needed to set things up. It supports Language Server Protocol or a custom HTTP interface; can infer library VHDL files likely belong to, besides working out mixed language dependencies, compilation order, interpreting some compilers messages and providing some static checks.

https://github.com/suoto/hdl_checker

#HDL #checker #LINT #verilog #VHDL #SV #python

Xilinx DMA PCIe tutorial by Roy Messinger

#Xilinx #Vivado #DMA #PCIE #BAR #PIPE #XDMA #AXI #driver

RgGen - a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Features:
◦ Generate source files related to CSR from register map specifications
◦ SystemVerilog RTL
◦ UVM RAL model
◦ Register map documents written in Markdown
◦ Register map specifications can be written in human readable format:
◦ Ruby with APIs to describe register map information
◦ YAML
◦ JSON
◦ Spreadsheet (XLSX, XLS, OSD, CSV)

https://github.com/rggen/rggen

#CSR #Automation #tool #ruby #wiki #UVM #RegisterMap

vcd2wavedrom - a python script to transform a VCD file to wavedrom format. The tool have flexible config in json format.

vcd2wavedrom in fact is tb2svg tool that improve performance of prepare documentation.

https://github.com/Toroid-io/vcd2wavedrom

#vcd #wavedrom #waveform #testbench #waves #documentation

Xilt - Command Line Tools for Xilinx Toolchain. Xilt assumes Xilinx ISE WebPack 14.7 is installed and only works on 64-bit Linux systems (this is a deliberate design decision since the ISE isn't officially supported on current versions of Windows).

Xilt can be used to:
◦ Build VHDL, Verilog and mixed mode FPGA projects.
◦ Runs xst, ngdbuild, map, par and bitgen all from one command invocation
◦ Filters output to show errors and warnings while suppressing all other messages
◦ Launch common Xilinx GUI tools (ISE, CoreGen and License Manager) without having to explicitly setup ISE environment paths
◦ Build places all intermediate files into a separate folder to keep your source folders clean

Usage example:

xilt build --device:xc6slx9-2-tqg144 myproj.vhd myproj.ucf

Link:
◦ Package
◦ Sources

#Xilinx #ISE #nodeJS #linux

Datasheet Scrubber - a utility that scrubs through large sets of PDF datasheets/documents in order to extract key circuit information. The information gathered is used to build a database of commercial off-the-shelf (COTS) IP that can be used to build larger SoC.

Datasheet Scrubber also define IP-XACT++, an extended version of IP-XACT, to encapsulate all the information needed for system generator, and port known IPs into the database. Doing this is really useful in finding the optimum SoC design based on user specifications.

Link:
◦ Description
◦ Sources

#datasheet #IPXACT #python #SoC #IP

Doulos is providing series of online training webinars including live interactive Q&A.

◦ April 3 - QEMU for Embedded System Developers
◦ April 8 - Integrating the Arm Cortex-M3 in a Xilinx FPGA
◦ April 15 - Getting Started with SystemVerilog
Functional Coverage
◦ April 17 - Why C is "The Language of Embedded"

For registration: https://www.doulos.com/content/training/webinars.php

#Doulos #onlinetraining #webinar #training #fpga #SV #digitaldesign #embeddedsystem #armcortex #xilinx

If you like Integrated Circuits, here is the NetFlix of IC Design: All past IEEE SSCS webinar videos & slides, ISSCC short courses & tutorials, and SSCSedu Lecture series are FREE (for a limited time), non-members can take advantage of this great offer.

FREE for a limited time: https://resourcecenter.sscs.ieee.org/

#webinar #onlinelearning #ieee #ic #sscs

Mentor's Functional Verification Training Series contains learning paths that help you master functional verification tools, and the development of test environments using HDL-based methodologies. Learn how to use SystemVerilog, HDL, UVM, CDC, ModelSim/Questa to verify and debug HDL designs in interactive mode or build batch mode scripts for fast simulations.

FREE for a 30-day access (hurry up to checkout until April 30): https://www.mentor.com/training/courses/functional-verification-training-library
Use promo code ODT-WECARE2020__30

PS: only corporate email are applicable

#Mentor #onlinetraining #webinar #training #verilog #SV #verification #FPGA

Yet Another VHDL tool performs parsing, semantic analysis, and elaboration. The goal is to at some point in the future integrate this with the yosys HDL synthesis tool.

Apparently, that's good starting point to develop your own VHDL parser.

https://github.com/rqou/yavhdl

#VHDL #parser #semantic #elaboration

Surelog tool providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench (System Verilog 2017 Pre-processor, Parser, UHDM Compiler. Provides IEEE Design/TB VPI and Python AST API).

Purpose: Linter, Simulator, Synthesis tool, Formal tools can use this front-end. They either can be developed as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk serialized models (UHDM).

https://github.com/alainmarcel/Surelog

Also see similar proj: https://github.com/alainmarcel/Surelog#similar-projects

#SystemVerilog #parser #semantic #elaboration

VSCode-SystemVerilog - VS Code extension provides features to read, navigate and write SystemVerilog code much faster.

Features
◦ Syntax Highlighting
◦ Code snippets for many common blocks
◦ Instantiate module from already indexed module
◦ Linter capabilites with simulators
◦ Fast real-time error identification through an integrated SystemVerilog parser and IntelliSense (IEEE 1800-2017)

https://github.com/eirikpre/VSCode-SystemVerilog

#SystemVerilog #VSCode #editor

How to logging FPGA resource usage by commit to commit?

Here good try to create a tool to track tranding LUT/FF/Freq by every commit:
https://github.com/mattvenn/logLUTs

#git #commit #stats #python