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Latency-insensitive Environment for Application Programming (LEAP) is a set of modules that provide a convenient platform for the development of FPGA-based applications.

http://www.leap-fpga.org/
RTL, Cmodel, and testbench for NVIDIA Deep Learning Accelerator (NVDLA). It's a free and open architecture that promotes a standard way to design deep learning inference accelerators.

https://github.com/nvdla/hw
Good solution to replace direct instantiating vendor-dependent clock buffer BUFG like that:

BUFG bufg_inst (
.I(clkin),
.O(clk_pcie)
);

instread to use the HDL-pragma like that (verilog):

(* clock_buffer_type = "BUFG" *) input clk_pcie;

Another BUFx type also aplicable for this pragma

#Xilinx #BUFG #primitives
Xilinx Ultrascale/US+ Cheatsheet for PLL/MMCM settings #Xilinx #US #US+ #PLLE #MMCME
Simple example for family-independent approach. Just pass -verilog_define ULTRASCALE as option to synth_design cmd. Or don't pass.
Excellent example for create constraint in case of using standalone (and cascaded!) clock multiplexors in FPGA:
https://www.xilinx.com/support/answers/59484.html

#Xilinx #BUFGMUX #XDC #ClockMux
XAPP888.PLL.Dynamic.Reconfiguration.pdf
455.2 KB
Good starting point how to work with dynamically tuned PLL/MMCM by DRP #XAPP888 #PLL #MMCM #Xilinx #PDF
XAPP888.PLL.Dynamic.Reconfiguration.zip
125.5 KB
Good starting point how to work with dynamically tuned PLL/MMCM by DRP #XAPP888 #PLL #MMCM #Xilinx #sources
Reusable Integration Framework for FPGA Accelerators (RIFFA) is a simple framework for communicating data from a host CPU to a FPGA via a PCI-E. RIFFA supports Windows/Linux, Altera/Xilinx, with bindings for C/C++, Python, MATLAB and Java.

https://github.com/KastnerRG/riffa
#PCI-E #DMA #Linux
One of my favorite part of UG949: RTL designer should know into which one primitives (and how many logic levels) infers strings of HDL
Open source tool for reading and writing Vivado design checkpoint (DCP) files. Its mission is to enable power users greater flexibility in customizing solutions http://www.rapidwright.io/ #DCP #Vivado
RapidWright_Enabling_Custom_Crafted.pdf
2.4 MB
RapidWright: Enabling Custom Crafted Implementations for FPGAs #RapidWright #Vivado #DCP
Yet another solution (IP+driver) for DMA over PCI-E for Linux/Windows Xilinx/Altera. http://xillybus.com/ #DMA #PCI-E #RIFFA #Xillybus
Useful code snippet for helping Super Logic Region (SLR) crossing in SSI Xilinx devices (based on slr crossing reg slice code):
https://github.com/nslmike/useful_stuff/blob/master/slr_crossing/slr_cross.v

#SLR #Xilinx #PR #verlog #crossing
Following command retrieves
the TEMPERATURE property from connected FPGA:
get_property TEMPERATURE [get_hw_sysmons]
To report all properties of HW_SYSMON use this in TCL console: report_property -all [lindex [get_hw_sysmons] 0]
#SysMon #TCL #XADC #Xilinx #Telemetry
2025/07/06 21:12:55
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