Did you know that Xilinx FPGA have Dynamically Reconfigurable Look-Up Table (LUT)?
It's called CFGLUT5

Note: This component occupies one of the eight LUT6 components within a CLBM.

#UG974 #Xilinx #recongif

This element is a runtime, dynamically reconfigurable, LUT5 that enables the changing of the function of the LUT during circuit operation. Using the CDI pin, a
new INIT to change the logical function.

Block RAM initialization content in VHDL|Verilog can be affected for both synthesis and simulation within the instantiated component. Modifying the values of the generic map (VHDL) or defparam (Verilog) affects both the simulation behavior and the implemented synthesis results. Inferred block RAM can be initialized as well.

#UG573 #Xilinx #BRAM #RAMB #defparam #INIT

Key differences between BlockRAM and UltraRAMwell.

#UG573 #Xilinx #BRAM #UltraRAM

Virtex Ultrascale+ VU13P dramatically boost DSP capacity (compare with VU9P)

Two approaches to getting device-DNA from FPGA using Vivado:
1. GUI based solution
2. TCL based solution

https://www.xilinx.com/support/answers/64178.html

AR#64178 #DNA #TCL